The present invention relates to a page buffer for a memory device and, more particularly, to a page buffer circuit of a Multi-Level Cell (MLC) memory device and a programming method.
Flash memory is generally classified into NAND flash memory and NOR flash memory. The NOR flash memory has a structure in which memory cells are respectively connected to a bit line and a word line, and therefore has good random access time characteristics. The NAND flash memory includes a plurality of memory cells connected in series and requires only one contact per cell string, and therefore has good characteristics for integration. Accordingly, the NAND structure is generally used for highly-integrated flash memory.
The well-known NAND flash memory device includes a memory cell array, a row decoder, and a page buffer. The memory cell array includes a plurality of word lines extending in rows, a plurality of bit lines extending in columns, and a plurality of cell strings respectively corresponding to the bit lines.
On one side of the memory cell array are disposed a string select line, the word lines, and the row decoder connected to a common source line. On the other side of the memory cell array is disposed the page buffer connected to the plurality of bit lines.
Recently, in order to further increase the level of integration of such flash memory, active research has been done into a multi-bit cell capable of storing a plurality of data in one memory cell. This type of a memory cell is called a MLC. A memory cell of a single bit is called a Single Level Cell (SLC).
The MLC generally has four or more threshold voltage distributions, and four or more data storage states corresponding to the threshold voltage distributions. A MLC into which 2-bit data can be programmed has four data storage states; [11], [10], [00] and [01]. The four data storage states correspond to threshold voltage distributions of each MLC.
For example, assuming that threshold voltage distributions of a memory cell are −2.7 V or less, 0.3 to 0.7 V, 1.3 to 1.7 V, and 2.3 to 2.7 V, [11] corresponds to −2.7 V or less, [10] corresponds to 0.3 to 0.7 V, [00] corresponds to 1.3 to 1.7 V, and [01] corresponds to 2.3 to 2.7 V. That is, if the threshold voltage of the MLC corresponds to one of the four types of the threshold voltage distributions, 2-bit data information corresponding to any one of [11], [10], [00] and [01] is stored in the MLC.
A MLC page buffer for a program and read operation of a flash memory device is described below.
FIG. 1 is a circuit diagram of a page buffer of a conventional MLC memory device.
Referring to FIG. 1, the MLC memory device includes a bit line selection unit 10 and a page buffer 20. The bit line selection unit 10 is for selecting a bit line according to an input address. This drawing is a simplified view in order to describe the page buffer 20 of the MLC memory device.
As illustrated in FIG. 1, the page buffer 20 includes a Most Significant Bit (MSB) latch unit 21 for programming the MSB of a 2-bit data, and a Least Significant Bit (LSB) latch unit 22 for programming the LSB of a 2-bit data.
The page buffer 20 of the memory device is included in each of a pair of even and odd bit lines, and has a number corresponding to a half of the bit lines of the memory device.
The bit line selection unit 10 includes first to fourth NMOS transistors N1 to N4.
The MSB latch unit 21 includes fifth to thirteenth NMOS transistors N5 to N13, first to third inverters IN1 to IN3, and a second PMOS transistor P2. The second and third inverters IN2 and IN3 constitute a first latch R1.
The LSB latch unit 22 includes fourteenth to twentieth NMOS transistors N14 to N20, fourth to sixth inverters IN4 to IN6, and a third PMOS transistor P3. The fifth and sixth inverters IN5 and IN6 constitute a second latch R2.
The page buffer 20 further includes a first PMOS transistor P1 for providing a precharge voltage for a program or read operation of the page buffer 20, a twenty-first NMOS transistor N21 for a read data output, and a seventh inverter IN7.
The construction of the data input is omitted from FIG. 1.
The operation of the page buffer 20 is described below.
In the program operation, a method of programming the LSB and MSB of a 2 bit data is used.
To this end, the first PMOS transistor P1 for supplying the precharge voltage is turned on, and the signal MSBRST set high to turn on the tenth NMOS transistor N10 of the MSB latch unit 21.
As the precharge voltage is applied, the eleventh NMOS transistor N11 is turned on to reset the first latch R1.
The LSB data is latched into the first latch R1 of the MSB latch unit 21.
The data latched in the first latch R1 is transmitted to the second latch R2 of the LSB latch unit 22 via the seventh NMOS transistor N7.
The data latched in the second latch R2 of the LSB latch unit 22 is transmitted to a memory cell connected to a bit line selected by the bit line selection unit 10, and is programmed into the memory cell.
As described above, after the LSB data is programmed, data verification is performed. The LSB data is read by the second latch R2 and stored therein.
Meanwhile, after programming the LSB, the MSB data is latched into the first latch R1 of the MSB latch unit 21.
The MSB data latched in the first latch R1 is compared with the LSB data read from the second latch R2 in order to determine whether programming has to be performed. The MSB data program is performed according to the determination result.
At this time, the fifth, sixth, fourteenth and fifteenth NMOS transistors N5, N6, N14 and N15 are compared the MSB data with the LSB in order to determine program.
Further, when reading data in the memory cell, the LSB latch unit 22 outputs a read data to the outside through the seventeenth NMOS transistor N17. The seventeenth NMOS transistor N17 is driven according to signal LSBPASS.
The MSB latch unit 21 outputs a read data to the outside through the eighth NMOS transistor N8. The eighth NMOS transistor N8 is driven according to signal MSBPASS.
As described above, the page buffer 20 for programming or reading the MLC comprises twenty-four elements, including sixteenth NMOS transistors, six inverters and two PMOS transistors, in which the MSB latch unit 21 and the LSB latch unit 22 are integrated.
The number of page buffers 20 corresponds to half the number of bit lines in the memory device as described above, and is an indispensable element for programming and reading of data.
Therefore, it is evident that if the capacity of a memory device is increased, the number of bit lines increases and the number of page buffers thus increases. Accordingly, in order to increase the level of integration, it is necessary to reduce the number of elements making up the page buffer.